Xilinx Serial Flash Loader

I just found the Serial Flash Loader (SFL) which allows you to program an Active Serial (AS) part (EPCSx) using the JTAG port, sparing you the need for a dedicated serial config header. According to AN370: this is made possible by a megawizard function which can be in your design or a stub design which is loaded expressly for doing the update. The programming tool in Quartus recognizes the 'JIC' files and selects a 'factory default SFL image' to accomplish the loading. There are two rows and thus two 'program' checkboxes, and I assumed you could simply un-check the FPGA part if you included SFL in your design, but the boxes are locked together. What is the trick for using the SFL embedded in your design instead of 'factory default SFL image'? -- Ben Jackson AD7GD. Ben Jackson wrote: >The programming tool in Quartus recognizes the 'JIC' files and selects >a 'factory default SFL image' to accomplish the loading.

Xilinx Serial Flash Loader

There are two >rows and thus two 'program' checkboxes, and I assumed you could simply >un-check the FPGA part if you included SFL in your design, but the >boxes are locked together. >>What is the trick for using the SFL embedded in your design instead of >'factory default SFL image'? What you see is exactly what you want.

U-Boot is an open source Universal Boot Loader that is frequently used in the Linux community. U-Boot provides the SF command to program serial flash.

Instal Aplikasi Linux Di Windows Phone there. It works for me. I assume the 'factory default SFL image' is simply a 'bootstrap' image for programming SFL. BTW once you've programmed your JIC image you need to power-cycle your board. Your custom FPGA image should then be configured as usual whilst allowing subsequent JIC programming. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd. Mark McDougall wrote: I should clarify - you simply need to instantiate the SFL mega-function in your design. Once you've built your image, use Convert Programming Files to produce a.JIC file which includes your.SOF.

You can then program the FPGA via JTAG with your new.SOF, then re-program with the.JIC which configures your EPCS device. Then power-cycle your board. Subsequent updates require reproducing the JIC from the SOF and re-configuring with the JIC. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd. On 2007-06-04, Mark McDougall wrote: >>I should clarify - you simply need to instantiate the SFL mega-function in >your design.

I thought the point of the megafunction was to add the SFL programming function to your image, so that you would not have to halt your device and send the 'stub' image over while programming the serial. That way the JIC programming would be transparent to the application until the next reset. With the programmer insisting on sending the shim, there seems to be no point to putting the SFL megafunction into your own design, since it will not be used. (Well, unless you were using it for direct serial access, but if it can't program via SFL you might as well use ASMI instead!) -- Ben Jackson AD7GD.

I just found the Serial Flash Loader (SFL) which allows you to program an Active Serial (AS) part (EPCSx) using the JTAG port, sparing you the need for a dedicated serial config header. According to AN370: this is made possible by a megawizard function which can be in your design or a stub design which is loaded expressly for doing the update. The programming tool in Quartus recognizes the 'JIC' files and selects a 'factory default SFL image' to accomplish the loading. There are two rows and thus two 'program' checkboxes, and I assumed you could simply un-check the FPGA part if you included SFL in your design, but the boxes are locked together. What is the trick for using the SFL embedded in your design instead of 'factory default SFL image'? -- Ben Jackson AD7GD.

Ben Jackson wrote: >The programming tool in Quartus recognizes the 'JIC' files and selects >a 'factory default SFL image' to accomplish the loading. There are two >rows and thus two 'program' checkboxes, and I assumed you could simply >un-check the FPGA part if you included SFL in your design, but the >boxes are locked together. >>What is the trick for using the SFL embedded in your design instead of >'factory default SFL image'? What you see is exactly what you want. It works for me.